Flash Technology

Manufacturers used DRAM as a cache to improve speed and endurance.  The cache may be designed using volatile or SLC NAND.  Improving cache hits makes access faster and improves endurance of MLC and TLC NAND, which make up the bulk of the memory.

However, the cache algorithm that is best for sequential write/random read applications such as video or logging, will be different for a system disks.  Consideration must also be given to data integrity in the event of power interruption and a disorderly shutdown.  Manufacturers will have various innovations to ensure that there is sufficient time on detection of a falling supply voltage to safely complete the last write command.  However, if this is over aggressive this can lead to problems with nuisance shut downs of memory.

With the exception of PATA and some operating modes of SD card formats, all modern high performance memory interfaces are serial using balanced pairs.  This has been shown to be highly fault tolerant which allow the data to be clocked at high speeds.  USB is a multi-drop serial bus capable of supporting speeds up to 640Mb/s.   SATA has separate read and write balanced pairs to form a single half duplex lane with a ATA application layer.  SAS has multiple full duplex lanes supporting a SCSI application layer.  PCIe can have up to 16 lanes and data streams are interleaved by bytes between channels.  The latest SATA standard and PCIe are usually faster than the fundamental memory technology and therefore not the limiting factor on performance.  At SSD we can help inform your choice of memory products to suit your application.